The use of high-k dielectrics in MOSFETs
In this article, I provide an overview of high-k dielectrics for use in MOSFETs. I discuss general considerations and associated tradeoffs when choosing a dielectric, as well as provide a comparison between the properties of silicon dioxide and high-k materials. I hope you enjoy!
Table of contents
· Motivation for high-k dielectrics
∘ SiO₂ has reached its minimum thickness
∘ Capacitance density and effective oxide thickness
· Dielectric selection rules
∘ General considerations
∘ Insights from electronic structure
· The defect effect
∘ Types of defects
∘ Defect-induced threshold voltage shift
· Quick aside: suggested criteria for optimal EOT
· Summary
· About the author
· Sources and further reading
Motivation for high-k dielectrics
If you’ve come this far, you know that the MOS capacitance plays an important role in modulating the inversion charge of the transistor channel and the current in the device. (See my article “Understanding MOSFETs with energy band diagrams” for a refresher.) It follows that the choice of dielectric forming the “O” of the MOS capacitor is also important.
SiO₂ has reached its minimum thickness
Silicon dioxide (SiO₂) is widely used as a dielectric for several reasons, including that it has a rather large band gap (E_g ~ 9 eV) and that it forms stable and relatively defect-free interfaces with both the silicon substrate and the material of the gate electrode.
However, with the increasing demands to scale down device area, the thickness of SiO₂ has reached the physical limit. Its minimum thickness is ~0.7 nm because at least two layers of neighboring oxygen atoms are needed to prevent the interfaces from overlapping. Also, for anything thinner than 3 nm, direct tunneling of charge carriers becomes a big issue, and the gate leakage becomes very large. The figure below (Lo et al., 1997) shows an example of gate leakage increasing significantly with the decrease in dielectric thickness.
Capacitance density and effective oxide thickness
As the device area is scaled down, a minimum gate capacitance must be maintained to have the same current drive. Thus, every loss of capacitor area has to be counterbalanced by an increase of capacitance density, the capacitance per area.
Capacitance density is usually measured in terms of equivalent oxide thickness (EOT), which gives the thickness of a SiO₂ dielectric required for a certain capacitance density. With the dielectric constant of SiO₂ k_SiO₂ equal to 3.9, the EOT of a capacitor using a higher-k dielectric (oxide with a higher dielectric constant) with thickness t_hk and dielectric constant k_hk can be calculated as shown below.
In order to maintain the capacitance for a smaller area, we can either
- Decrease the thickness of SiO₂ or
- Fnd a material with a larger dielectric constant (henceforth, a higher k)
The second is usually preferable because it allows us to use a larger physical thickness, and tunneling current can be minimized. This is the biggest motivation for using high-k materials.
Dielectric selection rules
However, just choosing a material with a higher k isn’t so straightforward, as there is usually a tradeoff between the k-value and band gap, and both are important for minimizing leakage current.
General considerations
As you may remember from solving the Schrödinger equation for a finite potential well, both the potential barrier width and height affect the probability of carriers tunneling through, but width and height can be more important at different applied voltages.
When we speak of width, this is controlled by the dielectric constant, as a higher k allows a greater thickness. When we speak of barrier height, this refers to the conduction band offset (CBO) between the oxide and the semiconductor, as it defines the barrier for injection of electrons into the oxide band. The valence band offset (VBO) is also important, but because the CBO tends to be smaller, it is usually the limiting factor.
For high biases (high electric field), the charge carriers get accelerated and gain kinetic energy, becoming hot as the frequency of collisions increases. These hot carriers have a greater chance of overcoming the barrier, resulting in thermionic emission. The height of the barrier matters more in this case.
For low biases, tunneling of lower-energy electrons through the barrier dominates, so the length of the tunneling path, which is the barrier width, matters more.
Regardless of whether barrier width or height is more important, the “must-have” criteria for CBO, VBO, and k-value are generally as follows (Choi et al. 2011):
- CBO, VBO > 1ev (block hot charge carriers)
- 10 < k < 30 (block direct tunneling)
Ideally, to reduce gate leakage current regardless of the biasing scheme, we would want both a sufficiently high dielectric constant and a high conduction band offset. But, again, there is a tradeoff that needs to be made since the dielectric constant tends to decrease as the band gap increases.
Insights from electronic structure
Recall that the dielectric constant is a measure of a material’s ability to store electrical energy in an electric field. It is related to the material’s polarizability, which is the amount of energy required to distort electron charge density (create dipoles, i.e., separate electron clouds from positively charged nuclei or separate the charges associated with anions and cations). Since the electric field created by the dipoles opposes the applied electric field, a higher polarizability means a higher dielectric constant, i.e., a more “attenuated” electric field. As such, materials with higher dielectric constants are better insulators and can store more electrical energy per unit volume.
The inverse relation between k-value and band gap can then be rationalized as follows: The band gap reflects the bonding-antibonding separation, so a small band gap means higher electronic polarizability associated with excitation into antibonding states, leading to higher k-value (Bersuker et al., 2004).
However, the inverse relationship isn’t linear by any means; many features of a dielectric’s material properties and electronic structure interact to give rise to the k-value and band gap. For example, a high-k dielectric formed by a transition-metal oxide has many properties attributable to open shell d-electrons (see left figure below). The weak π-type bonds they form contribute to a smaller band gap since the gap is determined by the splitting between bonding and antibonding orbitals. Also, the asymmetry and significant electron delocalization in d orbitals contribute to both greater ionic and electronic polarizability (due to the displacement of ions and electron clouds, respectively), leading to high k-values.
Even larger increases in k-value arise as the effects of ionic polarization become dominant (Bersuker et al., 2004) — another artifact of open shell d-electrons. Generally, d-p orbital overlap tends to give a higher ionic displacement compared to s-p or s-d. This phenomenon is very complicated, but in a nutshell,
- p orbitals have directional characteristics — they have lobe shapes pointing along specific axes.
- d orbitals have high complexity and asymmetry.
- d orbitals have higher energy than p orbitals, and the energy mismatch promotes electron density redistribution with d-p overlap.
All of this creates stronger ionic displacement. See Lucovsky et al. (2002) and Bersuker et al. (2004) for a more in-depth analysis of the transition-metal oxide MO energy level diagram and the role of d orbitals.
Aside from band gap and k-value, the reduced band offset energies associated with d orbitals can increase leakage current, as well as create another pathway for interfacial charge trapping (see right figure above). In this way, increased defects and leakage current add another potential tradeoff to consider when choosing a high-k dielectric.
On the other hand, one of the most important properties of SiO₂ is its nonrigid structure, which is the result of a wide range of stable Si-O-Si bond angles (see left figure below). This allows flexible alignment of silicate tetrahedrons, which reduces the probability of structural defects forming during growth.
Additionally, the sp-type Si-O bonding is responsible for the large band gap of SiO₂, as there is a large overlap of the s and p wave functions and, therefore, a larger splitting of the bonding and antibonding states (see right figure below).
The defect effect
Note that most of the information in this section is from Fleetwood et al. (1993) and Tewksbury & Lee (1994).
Types of defects
For some of the reasons mentioned in the section above, high-k dielectrics tend to have a higher density of defects, which can lead to instability in the MOSFET’s electrical properties, such as threshold voltage.
One type of defect is interface traps. These are more prevalent in high-k dielectrics because of the heterovalent nature of the semiconductor-dielectric interface, i.e., the semiconductor and dielectric have different numbers of valence electrons. Usually, there is a mismatch between the number of electrons available and the number required for covalent bonding, leading to charged-atom defects (Bera & Maiti, 2006).
Another type of defect is border traps, which are a special case of oxide traps closer to the interface. These are also more prevalent in high-k dielectrics due to their more rigid structure.
Together, interface and border traps can communicate with the semiconductor through different pathways, such as elastic tunneling from the conduction band, interface trap-assisted tunneling, and tunneling followed by lattice relaxation ([cb], [it], and [lr], respectively, in the figure above).
Defect-induced threshold voltage shift
Unfortunately, the presence of defects can contribute to threshold voltage shift. Consider the example in the figure below. Before stress is applied (left panel), the traps are occupied by electrons up to the semiconductor Fermi level E_Fs, so a lot of them are empty.
When a positive voltage is applied to the gate (middle panel), the Fermi level of the semiconductor rises relative to the metal, filling the trap states up to the new level. This is achieved by interface traps capturing inversion electrons and inversion electrons tunneling to border traps.
When the stress is removed (right panel), trap energies return to their original levels, and trapped carriers can be re-emitted to empty conduction band states.
The threshold voltage shift due to trapped charge can be broken down into two components: surface potential and band-bending.
The surface potential component is due to traps at energies within the silicon bandgap that change occupancy with the change in Fermi level and surface potential. On a microscopic level, the traps that comprise this component fill (red, green arrows in the middle panel below) and empty (red, green arrows in the right panel below) via [it] or [lr].
The band-bending component, which is driven by the change in voltage across the oxide, is due to traps that are lowered below the conduction band during stress and raised above it when the stress is removed. The traps that contribute to this component are therefore filled by [it] or [lr] but empty by [cb].
After the stress is removed and charge is re-emitted from the traps back into the channel, the re-emission has a broad distribution of time constants, so the shift in the threshold voltage relaxes over a long period of time.
Quick aside: suggested criteria for optimal EOT
Kar (2013, pp. 145–148) suggests criteria for choosing an optimal EOT by assessing the time constants of various processes associated with certain dielectric thicknesses. In particular, there are two threshold values of the EOT one must consider:
- EOT_threshold,min: the thickness delineating the thick (non-leaky)/intermediate tunnel MOS structure transition; defined in terms of minority carrier time constants
- EOT_threshold,maj: the thickness delineating the intermediate tunnel /Schottky tunnel MOS structure transition; defined in terms of majority carrier time constants
In particular,
For an EOT lower than the EOT_threshold,min, the time the minority carriers take to reach the semiconductor surface from the semiconductor bulk (=𝜏_generation+𝜏_drift) exceeds their time of tunneling from the semiconductor surface to the metal (𝜏_tunneling), as a result of which the minority carriers are drained away to the metal, no inversion layer forms at the semiconductor surface, and the minority carrier imref at the semiconductor surface gets pinned to the metal Fermi level
and
For an EOT lower than the EOT_threshold,maj, the time the majority carriers take to reach the semiconductor surface from the semiconductor bulk (=𝜏_relaxation + 𝜏_drift) exceeds their time of tunneling from the semiconductor surface to the metal (𝜏_tunneling), as a result of which the states on the semiconductor surface exchange carriers faster with the metal than with the semiconductor bulk, the occupancy of states at the semiconductor surface is determined by the metal Fermi level, and the majority carrier imref at the semiconductor surface gets pinned to the metal Fermi level
See Kar (2013, pp. 145–148) for more detailed information and accompanying visuals.
Summary
To summarize, the MOSFET is not only a voltage-operated device but a capacitance-operated device, as the capacitance of the oxide controls the inversion charge and, therefore, the channel conductivity and current. If we’re scaling down the device area but want to maintain the oxide capacitance, we can either decrease the oxide thickness or use a dielectric with a higher k. The latter is more desirable because low thicknesses are more vulnerable to leakage current.
There are many requirements for dielectrics that are suggested to replace silicon dioxide, including 1) forming a stable and good electrical interface with the silicon substrate, 2) having a high enough effective oxide thickness to prevent tunneling, which relates to a high k value, 3) having large enough band offset to minimize hot carrier injection, and 4) low density of interface and bulk states.
Silicon dioxide still triumphs in many of these areas, though its main downfall is that can’t offer a high enough thickness to prevent leakage current at the oxide capacitance required. While silicon dioxide remains a viable option for many applications, high-k dielectrics offer exciting possibilities for future advancements. The choice between the two depends on consideration of the specific requirements and trade-offs involved in each case.