Understanding MOSFETs with energy band diagrams
This article provides an overview of MOSFET principles of operation from an energy band perspective. Familiarity with energy band diagrams is assumed. For a refresher, see chapter 3 of Solid State Electronic Devices.
Table of contents
· Introduction
∘ What is a MOSFET
∘ What makes the MOSFET different
∘ Modes of operation
· Modulating V_G: z-axis POV
∘ Flatband/cutoff (V_G=0)
∘ Depletion/cutoff (0 < V_G < V_T)
∘ Inversion (V_G ≥ V_T)
∘ Accumulation (V_G < 0)
· Modulating V_G: x-axis POV
∘ Flatband/cutoff (V_G=0)
∘ Effect of increasing V_G
· Modulating VD: z-axis POV
∘ Inversion/linear (V_G ≥ V_T, V_D < V_G — V_T)
∘ Inversion/saturation (VG > VT, VD ≥VG — VT)
∘ Above pinch-off
· Modulating V_D: x-axis POV
∘ Effect of increasing V_D
∘ Observing pinch-off
· Summary
∘ Effect of V_G
∘ Effect of V_D
∘ Energy bands along the z-axis
∘ Energy bands along the x-axis
· About the author
· Sources and further reading
Introduction
Whether you’re looking at a bipolar junction transistor (BJT) or a field-effect transistor (FET) such as a MOSFET or JFET, most transistors operate by controlling the height of an energy barrier with an applied voltage. The operating principles of these devices are best understood in terms of energy band diagrams. Energy band diagrams can be viewed along different “axes” of the device, providing insight into the potential barriers carriers must overcome for current to flow.
Before we dive into energy band diagrams for MOSFETs, let’s remind ourselves of the structure of a MOSFET and what makes the MOSFET different from other transistors on a high level.
What is a MOSFET
MOSFET stands for Metal-Oxide-Semiconductor Field-Effect Transistor. The reason for this name will become clear as we discuss the MOSFET’s structure and operation.
The device is controlled by four terminals: gate (G), drain (D), source (S), and body (B). Current conduction between drain (D) and source (S) is controlled by a voltage applied to the gate (G) terminal. The body node gives the designer an extra degree of freedom, though it’s often tied to the same potential as the source. In turn, the source is usually tied to ground, so the gate and drain voltage primarily determine the mode of operation.
For n-channel MOSFETs (NMOS), the drain and source terminals are usually highly doped n-type material, while the body or substrate is lightly doped p-type material. For p-channel MOSFETs, it’s the opposite: the drain and source terminals are highly doped p-type material, while the body or substrate is lightly doped n-type material. For the sake of simplicity, throughout this article, we will only study the NMOS transistor.
The gate electrode is made of metal or poly-silicon, and is separated from the silicon body with a thin layer of a dielectric, such as silicon dioxide.
What makes the MOSFET different
The MOSFET plays a valuable role as an amplifier and switch in many electronic applications, from digital logic gates to power amplifiers. Several properties distinguish the MOSFET from other classes of transistors and other transistors in the FET family.
1. Voltage-controlled
Unlike the Bipolar Junction Transistor (BJT), whose conductivity is controlled by current, the conductivity of a MOSFET is controlled by the voltage applied to its terminals.
2. MOS capacitor
The MOSFET differs from its fellow FET family member, the JFET, in that the gate terminal is insulated from the body of the transistor by a thin layer of oxide, commonly silicon dioxide. This oxide capacitively couples the gate and the body of the transistor, forming a Metal Oxide Semiconductor (MOS) capacitor. In turn, this creates capacitances between the gate and body (C_GB), the gate and drain (C_GD), the gate and source (C_SD). Other parasitic capacitances can be included in such a model of a MOSFET, as shown below. Typically, when people refer to the “oxide capacitance” C_ox, this is a per-unit-area representation of C_GB.
The MOS capacitor plays an important role in modulating the current that flows through the induced channel. Therefore, we can consider the MOSFET not only a voltage-controlled device but also a capacitance-controlled device.
3. Large input impedance at low frequencies
The MOS capacitor is responsible for the larger input impedance of the MOSFET compared to the JFET. Like any other capacitor, the MOS capacitor blocks DC and low-frequency current. The absence of a DC path from the gate to source, drain, or substrate translates to high input impedance, as the gate voltage (relative to the source voltage) is our input terminal.
For a voltage-controlled device, high input impedance is an important property. When a device has a high input impedance, R_in = ΔV_in / ΔI_in is high, so a small change in input current ΔI_in (drawn from the source) is required to produce a change in the voltage at the input ΔV_in. Thus, the device draws very little current through its input, and the source can deliver its full signal voltage without a significant voltage drop across the device’s input.
4. Frequency dependence
As a capacitance-operated device, the MOSFET has a greater frequency dependence than a device like a BJT. This is why you might have come across low and high-frequency models of a MOSFET in textbooks. In actuality, there is capacitance between the gate and source (C_gs) and gate and drain (C_gd), but at low frequencies, we can treat the capacitors that model this as open, severing the path for DC current flow from gate to drain/source.
This has several implications. For example, that desirable high input impedance we just talked about will degrade at higher frequencies. At low frequencies, when the input impedance is still high, the MOSFET draws less power than the BJT. But at high frequencies, when the input impedance is significantly lower, the MOSFET may draw more power than the BJT, as the MOS capacitor allows the high frequency signal to pass from the gate to the source, drain, and channel.
Additionally, the capacitances can limit operating speed. In the case of a CMOS inverter, the time to discharge and charge the MOSFET capacitances will create a propagation delay, limiting the speed at which the inverter can respond to a change at its input (the maximum switching frequency).
Modes of operation
Now, we’re ready to delve into the MOSFET’s principles of operation! We will focus on n-channel MOSFETs since they are easier to work with and more common.
For each case, we will examine the energy bands along the z axis (the energy barriers formed at the MOS interfaces) and the energy bands along the x axis (the energy barriers formed between source, drain, and gate).
Modulating V_G: z-axis POV
When looking along the z-axis, we are effectively holding x constant, i.e., examining the MOS interface at a particular point x along the channel. In the case that V_D = 0V (more generally, when V_S = V_D) and the bias is uniform across the channel, then the cross section we are examining shouldn’t change with x anyways.
Therefore, energy band diagrams along the z-axis are most useful for examining how V_G changes the operation of the MOSFET, and whether inversion can occur across the length of the channel.
Flatband/cutoff (V_G=0)
Let’s first consider the flat band condition, when no gate voltage is applied and the energy bands of the substrate are flat at the semiconductor-oxide interface. We will assume ideal conditions, one of which is that the modified work functions of the metal and semiconductor (qΦ_s and qΦ_m) are equal. Otherwise, there would be band bending at equilibrium to accommodate the work function difference.
To orient ourselves, let’s refer to the figure below and compare the superimposed z axes in the MOSFET cross-section (left) and energy band diagram (right). In the energy band diagram, the leftmost point on the semiconductor side (z=0) corresponds to some point at the surface of the semiconductor. The rightmost point on the semiconductor side corresponds to somewhere deep in the bulk.
The figure is not drawn to scale, but for silicon dioxide, the conduction band offset is ~3eV, and the valence band offset is ~5eV. These form energy barriers for electrons and holes, normally preventing them from passing through the dielectric (gate leakage current). We will discuss this more later.
The depletion region width at the drain and source is the same as that for an unbiased PN junction. However, barely any depletion region forms at the semiconductor-oxide interface. There definitely isn’t an inversion channel since a depletion region must form before inversion (the attraction of electrons to the surface) can occur.
As there is no channel, there is no conductive pathway between the source and drain, and the drain current is essentially zero. Since no current flows, we are in cutoff mode — the “off state” of the MOSFET.
Depletion/cutoff (0 < V_G < V_T)
The application of a gate voltage V_G determines whether an inversion region will form or just a depletion region. The first case is when the applied gate voltage is less than the threshold voltage V_T; for this case, the drain voltage doesn’t matter.
The positive gate voltage effectively deposits a positive charge on the metal. This repels holes of the p-type material away from the surface, leaving behind the p-type’s uncovered acceptors and, therefore, a negative bound charge. In the resulting depleted region, the material looks more intrinsic. We can see this in the energy band diagram as the intrinsic energy level E_i moves closer to the semiconductor Fermi level E_Fs near the surface, and the bands bend down.
In the figure below, you’ll see two potentials, ϕ_F(x) and ϕ_s(x), defined relative to the equilibrium position of E_i. (To obtain a quantity in terms of energy, we multiply by the charge of an electron q.) These are useful for describing band bending at the MOS interface. ϕ_F(x) measures the position of the Fermi level below the intrinsic level E_i for the semiconductor deep in the bulk. This quantity indicates how strongly p-type the semiconductor is.
The notation is confusing, but ϕ_s(x) is not the same as Φ_s (capital phi), which is the modified work function of the semiconductor. The surface potential ϕ_s(x) tells us the extent of band bending at the surface for our given point x along the channel. For the flat band condition of an ideal MOS that we examined above, ϕ_s=0. In the case of depletion mode, ϕ_s > 0, but it is only enough to make E_i bend down to E_Fs, not beyond it. In other words, 0 < ϕ_s < ϕ_F.
Since there is still no inversion channel, only a depletion region, we’re still in cutoff mode.
Inversion (V_G ≥ V_T)
Once the gate voltage exceeds the threshold voltage, the metal’s positive charge is enough to not only deplete the surface region of free holes but also attract free electrons. Therefore, an inversion region is formed at the surface, and it starts to look like n-type material.
In the band diagram, we see this as the intrinsic level E_i bending below the semiconductor’s Fermi level E_Fs at the surface. In other words, the surface potential ϕ_s(x) > ϕ_F(x) is enough to make E_i bend down beyond E_Fs.
A distinction can be made weak and strong inversion. Weak inversion is simply when ϕ_s(x) > ϕ_F(x). Strong inversion is when the surface potential is greater than twice ϕ_F(x), i.e., ϕ_s(x) > 2ϕ_F(x). This condition indicates the surface is as strongly n-type as the substrate is p-type, i.e., E_i lies as far below E_F at the surface as it is above E_F deep in the bulk.
Even though the surface is inverted under weak inversion, you might consider a true n-type channel to only exist once we reach strong inversion. When an n-channel MOSFET is in weak inversion, the drain current is determined by diffusion of electrons from the source to the drain. The drift current is negligibly small due to the low lateral electric field and small electron concentration.
Accumulation (V_G < 0)
So far, we’ve only considered the application of positive gate voltage. But what happens when we apply V_G < 0?
Well, instead of repelling holes away from the surface, we’ll attract even more mobile holes from the p-type substrate to the surface! No depletion region will form, so there definitely won’t be an inversion channel.
Note that even though there are plenty of mobile charges at the surface in accumulation mode, we won’t have a pathway for conduction as we do in inversion mode. Remember that an inversion channel serves as a sort of bridge across the device, connecting the n-type source and drain regions with a channel of mobile electrons.
In the case of accumulation, where there is instead an excess of mobile holes near the surface, no current flows between the n-type source and drain regions; the excess of majority carriers prevents current flow rather than facilitates it. A MOSFET in accumulation mode functions similarly to an NPN BJT, where the source and drain are insulated by two reverse-biased PN junctions.
Though accumulation mode isn’t used in typical MOSFETs, specialized designs such as accumulation-mode MOSFETS (AMOSFETs) rely on accumulation of majority carriers for the device’s “on” (current-conducting) state.
Modulating V_G: x-axis POV
We can also view of the energy bands along the x-direction. Let’s first take another look at the flatband condition, when no voltage is applied.
Flatband/cutoff (V_G=0)
In the figure below, only the conduction band is shown because we are discussing an n-channel MOSFET for which the current is carried by electrons in the conduction band. The upper part shows the n-type source and drain regions, and the p-type channel region as if they were separate, so “before contact.”
In equilibrium, and “after contact,” the Fermi level is constant, so the source and drain energy bands must drop in energy (or, equivalently, the channel energy must rise) until E_F is constant. The alignment of the Fermi levels occurs because electrons flow from high to low Fermi level. In this case, the resultant potential difference is just the built-in potential V_bi, just like for an unbiased PN junction.
Here, the energy barriers at the source-channel and drain-channel junctions prevent net current flow across the channel.
Effect of increasing V_G
A positive gate voltage lowers the barrier to carriers that want to traverse the channel. By applying a positive gate voltage, we increase the potential of the channel, which lowers the conduction band energy at the channel relative to the drain and source. Because the barrier to electrons is lower, they have the ability to traverse the channel.
But because the drain and source are equal in potential, there is no net traversal — flow of electrons from source to drain is balanced by flow from drain to source. In the next section, we’ll examine the importance of the drain voltage in creating a net current flow.
Modulating VD: z-axis POV
Once the gate voltage biases the MOSFET in the inversion regime (V_G ≥ V_T), V_D determines the mode of operation.
Inversion/linear (V_G ≥ V_T, V_D < V_G — V_T)
The inversion regime can operate the MOSFET in linear or saturation mode, depending on the drain voltage V_D. V_D effectively controls the “uniformity” of the channel depth, where the depth refers to the inversion charge density.
Since the MOS acts like a capacitor, the total charge stored by the capacitor Q_t is roughly proportional to the potential across the oxide V^t_ox.
As we’re only concerned with the inversion charge Q_i that makes up the channel, not the total charge of inversion and depletion (Q_t = Q_i + Q_d), we need to examine the potential across the oxide due to the inversion charge, V^i_ox. This is determined by the difference between the channel and the overdrive voltage (V_G — V_T); up to V_T, we mainly have depletion, and only the excess of V_G over V_T produces inversion.
If we increase the channel potential V_ch at a point x, the voltage across the oxide will decrease, and the “charge stored” will decrease at that point as well.
The drain voltage is still relatively small in linear mode, so the channel is approximately uniform in depth. Since the inversion charge density depends mostly on the gate voltage when V_D is small, the channel resistance is gate-voltage‐dependent, and the MOSFET acts like a voltage-controlled resistor.
Inversion/saturation (VG > VT, VD ≥VG — VT)
On the other hand, if V_D is large enough, we can no longer treat the channel depth as uniform. We can think about this in two ways:
- As we approach the drain, the channel potential becomes more positive, so the potential across the oxide decreases. Therefore, the charge on the capacitor plates must decrease as well.
- The charge on a small volume of the gate is balanced by charge in the semiconductor, which is the sum of the depletion charge and the inversion charge. The larger drain voltage makes the drain-substrate PN junction more reverse-biased, increasing the depletion charge toward the drain. Consequently, the inversion charge decreases to balance out the increased depletion charge.
A special case is when V_D equals the overdrive voltage, and the inversion charge density becomes zero at the drain. At this point, the channel is “pinched off.”
Once this happens, we enter saturation, and the drain current I_D is mostly independent of V_D — further increasing the drain voltage won’t affect the current. I_D is said to saturate and the MOSFET acts as a voltage-controlled current source.
Above pinch-off
As V_D is increased further, the point where the channel pinches off moves closer the source, and the channel no longer extends all the way. However, this doesn’t mean that the drain current goes to zero. The positive voltage applied to the drain reverse biases the drain-body junction even more than the source-body junction. Therefore, the depletion region grows larger — both the thinner layer of positively charged uncovered donors and the thicker layer of negatively charged uncovered acceptors.
The x component of the electric field has lines that originate on the positive uncovered donors and terminate on electrons in the inversion channel. This electric field sweeps electrons from the channel to the drain. The drain current remains constant as the drain voltage increases because it is primarily a drift current.
Modulating V_D: x-axis POV
Effect of increasing V_D
To summarize the effect of the drain voltage, we can look at the energy bands along the x direction again. As you can see, the drain voltage increases the electric field felt by electrons swept from the channel to the drain, as the slope here is increasing in magnitude. Therefore, in saturation, the primary current is drift current (due to the electric field), whereas before, it was diffusion current (due to the concentration gradient of carriers along the x-axis).
This figure also illustrates why the drain current saturates with increasing drain voltage. The source-channel barrier is what limits the current. Electrons that make it over the barrier flow down hill and out the drain. Increasing the drain voltage shouldn’t really affect this barrier, so it shouldn’t increase the current.
Observing pinch-off
One final thing to notice is we can tell where the channel is pinched off by seeing where the quasi-Fermi level for electrons, F_n, coincides with the intrinsic energy level E_i, which indicates that the region is depleted of electrons at that point. In theory, this is the part of the channel where the inversion charge would no longer exist.
Summary
Remember that this summary is for an n-channel MOSFET (NMOS), i.e., where the substrate is p-type and the source and drain regions are n-type. To get the behavior of a p-channel MOSFET (PMOS), simply reverse the signs. E.g., accumulation mode occurs for V_G > 0, inversion occurs for V_T < V_G < 0, etc.
Effect of V_G
- The application of a gate voltage V_G determines whether an accumulation region (excess of majority holes), depletion region (uncovered, negatively-charged acceptor ions), or inversion region (excess of minority carrier electrons) will form at the oxide-semiconductor interface (the surface). To get inversion, you must first have depletion.
- When V_G < 0, the MOSFET is in accumulation mode, meaning an excess of holes is attracted from the p-type substrate to the surface. There is no conductive pathway between the n-type source and drain regions, so no current flows (cutoff).
- When 0 < V_G < V_T, the MOSFET is in depletion mode, meaning holes of the p-type substrate are repelled from the surface and a depletion region is formed. Since only bound negative charges exist in this region, not mobile electrons, there is still no conductive pathway between the source and drain. Therefore, the MOSFET is still in cutoff, and no current flows.
- When V_G ≥ V_T, the MOSFET is in inversion mode. The gate voltage is great enough to not only repel holes from the surface but also attract free electrons. An inversion channel is formed by the free electrons, though a net current only flows with the application of V_D.
Effect of V_D
- Once the gate voltage biases the MOSFET in the inversion regime (V_G ≥ V_T), V_D determines the mode of operation. V_D effectively controls the “uniformity” of the channel depth, where the depth refers to the inversion charge density.
- For (V_G ≥ V_T, V_D < V_G — V_T), the MOSFET is in linear mode. Since V_D is still relatively small, the channel is approximately uniform in depth. Since the inversion charge density depends mostly on V_G when V_D is small, the channel resistance is gate-voltage‐dependent and the MOSFET acts like a voltage-controlled resistor. The drain current I_D varies ~linearly with V_D.
- For (V_G ≥ V_T, V_D ≥ V_G — V_T), the MOSFET is in saturation mode. The channel reaches pinch-off at the drain end, and the drain current I_D saturates, i.e., it no longer increases with increasing V_D. Thus, the MOSFET acts as a voltage-controlled current source.
Energy bands along the z-axis
- When looking along the z-axis, we examine the MOS interface at a particular point x along the channel. Recall that the channel potential V_ch(x) varies from V_S = 0V at the source end to V_D = V_D at the drain end. Since V_G is constant across the channel, energy band diagrams along the z-axis are most useful for examining how V_G changes the operation of the MOSFET and whether inversion can occur across the length of the channel, regardless of V_ch(x).
- Along the z-axis, the energy barriers of interest are the conduction and valence band offset between the semiconductor and oxide. These barriers make it hard for carriers to go from the semiconductor side to the oxide, assisting with the prevention of gate leakage current. The barriers are primarily determined by the choice of metal and semiconductor, not the biasing scheme.
- Band bending at the MOS interface tells us more about the MOSFET’s mode of operation. By applying a gate voltage V_G, we effectively deposit charge on the metal. Band bending at the MOS interface (described by the surface potential ϕ_s) tells us how charge is induced in the semiconductor in response to the metal’s charge.
- Accumulation (ϕ_s < 0): bands bend upward so that the surface looks even more p-type
- Flat band (ϕ_s = 0): no band bending
- Depletion (0 < ϕ_s < ϕ_F): bands bend downard, but not enough for E_i to bend below E_F (only enough for surface to look intrinsic)
- Inversion (ϕ_s > ϕ_F): bands bend downard, enough for E_i to bend below E_F (enough for the surface to start looking n-type)
Energy bands along the x-axis
- Along the x-axis, the energy barriers of interest are at the source-channel and drain-channel junctions (equivalently, source-body and drain-body junctions). Therefore, energy bands along the x-axis are most useful for determining how applying a drain voltage V_D changes the MOSFET's mode of operation.
- Though applying V_G>V_T to the gate of an NMOS lowers the barrier to carriers that want to traverse the channel, there is no net current flow. V_D is required to create a mismatch in the barriers at the source-channel and drain-channel junctions and induce net current flow from drain to source.
- Application of V_D>0 makes the drain-channel barrier higher than the source-channel barrier. Electrons diffuse from the source to the channel (by overcoming the barrier), then drift under the increasing electric field from the channel to the drain.
- The source-channel barrier is what limits the current, so the drain current saturates (reaches a near-constant maximum) with increasing drain voltage.
Sources and further reading
https://www.cs.cmu.edu/afs/cs/academic/class/15849c-s02/www/papers/dwgtext.pdf
https://worldscientific.com/doi/epdf/10.1142/9789814571746_0003
https://www.chu.berkeley.edu/wp-content/uploads/2020/01/Chenming-Hu_ch5-1.pdf
https://www.worldscientific.com/doi/pdf/10.1142/9789811267277_0003
